1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a defective bit cell can be substituted by a redundant bit cell.
2. Description of the Related Art
In these days, a semiconductor memory device has increased integration with the result that a fabrication yield tends to be deteriorated. A latest semiconductor memory device stores excessive redundant bit cells in a memory cell array and substitutes one of the stored redundant bit cells for a defective bit cell to thereby prevent deterioration of a fabrication yield. The substitution of a redundant bit cell for a defective bit cell is carried out usually by a process of breaking a fuse that has been formed beforehand by laser beam irradiation and switching a connection in a circuit.
In the process, an additional interconnection layer to be used as a fuse is not excessively formed. In general, as a fuse is used the same layer as a layer to be used as a bit line in the case of DRAM, a grand line in the case of SRAM, or a word line in the case of a non-volatile memory such as EPROM and a flash memory.
In most cases, such a fuse is composed of heavily phosphorus-doped polysilicon; tungsten silicide (WSi) or tungsten polycide. A process for fabricating such a fuse is designed not to increase the number of fabrication steps, as will be mentioned hereinbelow.
Hereinbelow is explained a first prior art with reference to FIGS. 1 and 2A to 2C. FIG. 1 is a top plan view illustrating a fuse of a conventional DRAM, and FIGS. 2A to 2C are cross-sectional views taken along the line C--C in FIG. 1 and show a process for fabricating the fuse illustrated in FIG. 1.
First, on a p type silicon substrate 1 is formed an oxide layer 2 for isolation of elements. Then, there is formed an n channel MOS transistor including a gate oxide layer 3, a gate 4, and n type diffusion layers 5a and 5b. Subsequently the resultant structure is covered with a first interlayer insulative layer 6.
Then, there is formed a first contact hole 7 reaching the n type diffusion layer 5a through the first interlayer insulative layers 6. Subsequently, a bit line 8 composed of tungsten silicide (WSi) is formed on an inner surface of the contact hole 7. A fuse 9 is formed on the first interlayer insulative layer 6 simultaneously with the bit line 8. Then, the resultant is entirely covered with a second interlayer insulative layer 10.
Then, there is formed a capacitive contact hole 11 reaching the n type diffusion layer 5b through the first and second interlayer insulative layers 6 and 10. Subsequently, there is formed an accumulation electrode 12 coming to contact with the n type diffusion layer 5b through the contact hole 11. The accumulation electrode 12 is covered over an exposed surface thereof with a capacitive insulative layer 13, which in turn is wholly covered with a facing electrode 14. Then, as illustrated in FIG. 2A, the resultant structure is covered with a third interlayer insulative layer 16.
Then, there are formed a plurality of second contact holes 17 reaching a n type diffusion layer 5c and the fuse 9. Though not illustrated, the second contact holes 17 reach a p type diffusion layer, a word line, a bit line, and the facing electrode, and hence they are exposed to the outside. Then, the resultant is wholly covered with a barrier layer 19 made of metal. As illustrated in FIG. 2B, the resultant is further covered with a tungsten (W) layer 20 so that the second contact holes 17 are all filled.
Then, the tungsten layer 20 is anisotropically etched back to thereby form a tungsten plug 21 within in the second contact hole 17. Subsequently, the resultant is wholly covered with a metal layer, which is in turn patterned to thereby form metal interconnections 24, as illustrated in FIG. 2C.
The reason why the tungsten plug 21 is formed is as follows. With increasing minuteness of a semiconductor memory device, an aspect ratio of a contact hole becomes greater. For that reason, even if it is intended to make an electrical connection to the n type diffusion layer 5c through the second contact hole 17 only with metal, metal has a poor property of covering a step, and hence reliability of the connection cannot be obtained. Thus, it is necessary to bury the contact hole with tungsten having a superior property of covering a step.
Through the above mentioned steps, a fuse is formed. In the device illustrated in FIG. 2C, a current runs through the metal interconnection 24, the tungsten plug 21, the fuse 9 made of tungsten silicide, the tungsten plug 21, and the metal interconnection 24 in this order.
As mentioned earlier, a fuse has been composed of polysilicon, silicide or polycide in order to make it unnecessary to add extra steps for fabricating a fuse. Japanese Unexamined Patent Public Disclosure No. 62-119938 has suggested using a fuse made of tungsten (W), molybdenum (Mo), chromium (Cr) or vanadium (V) which can be melted and thus broken with low energy and whose oxides are volatile, in place of polysilicon, silicide and polycide. However, additional steps are required to construct a fuse with W, Mo, Cr or V.
In the first prior art mentioned with reference to FIGS. 1 and 2A to 2C, a fuse is composed of phosphorus-doped polysilicon, tungsten silicide or tungsten polycide, all of which have a layer resistance of a few hundreds ohms per a unit area. Accordingly, an operational speed of a memory device made of such materials is reduced in comparison with a memory device made of tungsten having a layer resistance of approximately 0.1 ohm per a unit area.
In the second mentioned prior art, No. 62-119938, a fuse is composed of metal such as tungsten. However, in this prior art, an interconnection associated with a fuse is composed also of tungsten having a greater resistivity than aluminum, and hence the same problem as that of the first prior art arises. In addition, the second prior art has to additionally include a photolithography step and an etching step for forming a tungsten layer and patterning a fuse, and accordingly it increases the number of fabrication steps.